PRACE Best Practice Guide on Modern Accelerators

The 2021 PRACE Best Practice Guide on “Modern Acceleratots” [1], elaborated as part of the PRACE-6IP project I manage for the University with Dr. Ezhilmathi Krishnasamy (Mathi for short) is out ! Announcement for this report was also done on Scientic Computing World, a global publication dedicated to the computing and information technology needs of scientists and engineers.

Abstract: Hardware accelerators offer certain advantages over general-purpose Central Processing Units (CPUs) as they provide a greater computational throughput when applications exhibit high degrees of data parallelism, due to their highly parallel architectural design and high-bandwidth memory systems. These specialized chips are usually more energy-efficient, i.e. are capable of delivering much higher compute performance as compared to CPUs at the same power cost. These characteristics make accelerator technologies appealing both for system vendors and users. The PRACE Best Practice Guide (BPG) on “Modern Accelerators” follows the style of previously published guide on “Modern Processors”, and provides an update on certain contemporary accelerator technologies, again, in a hybrid fashion of a field guide and a textbook.

More specifically, this guide starts with introducing the architectures of considered accelerator technologies, namely:

• Graphics Processing Units (GPUs)
• Field-Programmable Gate Arrays (FPGAs)
• Vector processors

This is then followed by a discussion on their suitability for different HPC applications, and a description of their accompanying emerging programming models (e.g. CUDA, SYCL, HIP, etc.) and development environments. This BPG then outlines certain hints and best practices for application porting and tuning built upon the available literature and the expertise of authors involved.

Finally, the guide provides a brief information on the available hardware infrastructure at PRACE HPC sites featuring the discussed accelerator technologies, and concludes with a description of the case applications used.

1. J. Bispo, J. G. Barbosa, P. F. Silva, C. Morales, M. Myllykoski, P. Ojeda-May, M. Bialczak, M. Uchronski, A. Wlodarczyk, P. Wauligmann, E. Krishnasamy, S. Varrette, and S. Lürs, “PRACE Best Practice Guide 2021: Modern Accelerators,” PRACE aisbl, Jun. 2021.
   
   BibTeX URL Abstract
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   BibTeX

   @techreport{PRACE_BPG_ModernAccelerators2021,
     author = {Bispo, J. and Barbosa, J.G. and Silva, P.F. and Morales, C. and Myllykoski, M. and Ojeda-May, P. and Bialczak, M. and Uchronski, M. and Wlodarczyk, A. and Wauligmann, P. and Krishnasamy, E. and Varrette, S. and L\"urs, S.},
     title = {{PRACE Best Practice Guide 2021: Modern Accelerators}},
     institution = {PRACE aisbl},
     year = {2021},
     month = jun,
     url = {https://prace-ri.eu/training-support/best-practice-guides/modern-accelerators/},
     note = {\href{https://prace-ri.eu/wp-content/uploads/Best-Practice-Guide-Modern-Accelerators.pdf}{pdf}}
   }
   

   Download the 2021 Best Practice Guide on "Modern Accelerators" (PDF)

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